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RFP45N06LE, RF1S45N06LESM
Data Sheet October 1999 File Number 4076.2
45A, 60V, 0.028 Ohm, Logic Level N-Channel Power MOSFETs
These are N-Channel enhancement mode power MOSFETs manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA49177.
Features
* 45A, 60V * rDS(ON) = 0.028 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFP45N06LE RF1S45N06LESM PACKAGE TO-220AB TO-263AB BRAND FP45N06L F45N06LE
Symbol
D
G
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel i.e., RF1S45N06LESM9A.
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE DRAIN (FLANGE)
JEDEC TO-263AB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 407-727-9207 | Copyright (c) Intersil Corporation 1999.
RFP45N06LE, RF1S45N06LESM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFP45N06LE, RF1S45N06LESM 60 60 10 45 Refer to Peak Current Curve Refer to UIS Curve 142 0.95 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA TO-220, and TO-263 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 48V, ID = 45A, RL = 1.07 (Figures 20, 21) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 13) VGS = VDS, ID = 250A (Figure 12) VDS = 55V, VGS = 0V VDS = 50V, VGS = 0V, TC = 150oC VGS = 10V ID = 45A, VGS = 5V (Figure 11) VDD = 30V, ID = 45A, RL = 0.67, VGS = 5V, RGS = 2.5 (Figures 10, 18, 19) MIN 60 1 TYP 20 150 55 90 107 58 2.4 2150 640 240 MAX 3 1 250 10 0.028 215 185 135 75 3.0 1.05 80 UNITS V V A A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz (Figure 14)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse test: pulse width 80s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). SYMBOL VSD trr ISD = 45A ISD = 45A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 155 UNITS V ns
2
RFP45N06LE, RF1S45N06LESM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER
Unless Otherwise Specified
50
1.0 0.8 0.6 0.4 0.2 0 ID, DRAIN CURRENT (A)
40
30
20
10
0
25
50 75 100 125 TC , CASE TEMPERATURE (oC)
150
175
0 25
50
75 100 125 TC, CASE TEMPERATURE (oC)
150
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101
ZJC, NORMALIZED THERMAL IMPEDANCE
0.01 10-5
10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
IDM, PEAK CURRENT CAPABILITY (A)
TC = 25oC TJ = MAX RATED
500
VGS = 10V
TC = 25oC
ID, DRAIN CURRENT (A)
100 100s
VGS = 5V
100
1ms 10 10ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 200
THERMAL IMPEDANCE MAY LIMIT CURRENT IN THIS REGION
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
= I25
10 10-5
175 - TC 150 100 101
10-4
10-3 10-2 10-1 t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
3
RFP45N06LE, RF1S45N06LESM Typical Performance Curves
200 IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) 80
Unless Otherwise Specified (Continued)
100 VGS = 10V VGS = 5V VGS = 4V
STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
60
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 3.5V
40 VGS = 3V 20 VGS = 2.5V 0
1 0.01
0
1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V)
6.0
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
100 VDD = 15V 80 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -55oC 25oC rDS(ON), DRAIN TO SOURCE
80 ID = 45A ON RESISTANCE (m) 60 ID = 11.25A 40 ID = 22.5A 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ID = 90A
175oC
60
40
20
0
0
1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V)
6.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
600 VDD = 30V, ID = 45A, RL = 0.67 500 SWITCHING TIME (ns) td(OFF) 400 tf 300 200 100 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () td(ON) NORMALIZED ON RESISTANCE tr
2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 45A 2.0
1.5
1.0
0.5 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4
RFP45N06LE, RF1S45N06LESM Typical Performance Curves
1.2
Unless Otherwise Specified (Continued)
1.2 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
VGS = VDS, ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6
0.9
0.4 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0.8 -80
-40
0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
3000 2500 C, CAPACITANCE (pF) CISS 2000 1500 1000 COSS 500 0 CRSS 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
60 VDS , DRAIN TO SOURCE VOLTAGE (V) VDD = BVDSS 45 RL = 1.3 IG(REF) = 1.3mA VGS = 5V 30 PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS I G ( REF ) 20 --------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 --------------------I G ( ACT ) 2.50 VDD = BVDSS 3.75 5.00 VGS , GATE TO SOURCE VOLTAGE (V)
15
1.25
0
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
5
RFP45N06LE, RF1S45N06LESM Test Circuits and Waveforms
(Continued)
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS RL VDD VDS Qg(10) OR Qg(5)
+
Qg(TOT)
VGS
VGS = 20V VGS = 10V FOR L2 DEVICES VGS = 10V VGS = 5V FOR L2 DEVICES
VDD DUT Ig(REF)
VGS VGS = 2V 0 VGS = 1V FOR L2 DEVICES Qg(TH)
Ig(REF) 0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
6
RFP45N06LE, RF1S45N06LESM PSPICE Electrical Model
SUBCKT 45N06LE 2 1 3 ;
CA 12 8 3.73e-9 CB 15 14 3.73e-9 CIN 6 8 2.08e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 10/25/95
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
ESG 6 8 + LGATE GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 4.0e-9 LGATE 1 9 6.0e-9 LSOURCE 3 7 3.0e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.75e-3 RGATE 9 20 1.0 RLDRAIN 2 5 40 RLGATE 1 9 60 RLSOURCE 3 7 30 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 6.15e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),4))} .MODEL DBODYMOD D (IS = 1.70e-12 RS = 3.20e-3 TRS1 = 1.75e-3 TRS2 = 1.75e-6 CJO = 2.55e-9 IKF = 13 XTI = 5.2 TT = 7.00e-8 M = 0.47) .MODEL DBREAKMOD D (RS = 1.70e-1 IKF = 0.1 TRS1 = 2.00e-3 TRS2 = 8.00e-7) .MODEL DPLCAPMOD D (CJO = 2.00e-9 IS = 1e-30 VJ = 1.1 M = 0.83 N = 10) .MODEL MMEDMOD NMOS (VTO = 2.00 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.0) .MODEL MSTROMOD NMOS (VTO = 2.42 KP = 128 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.60 KP = 0.01 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10.0 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.13e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 6.00e-5) .MODEL RSLCMOD RES (TC1 = 2.00e-3 TC2 = 1.00e-6) .MODEL RSOURCEMOD RES (TC1 = 2.00e-3 TC2 =-1.00e-5) .MODEL RVTHRESMOD RES (TC1 = -2.50e-3 TC2 = -8.50e-6) .MODEL RVTEMPMOD RES (TC1 = -2.00e-3 TC2 = 5.00e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.3 VOFF= -2.5) VON = -2.5 VOFF= -5.3) VON = -1.4 VOFF= 0.5) VON = 0.5 VOFF= -1.4)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
+
-
EBREAK 11 7 17 18 66.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
RFP45N06LE, RF1S45N06LESM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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